1. Field of the Invention
This invention is concerned with data transfer in a multi-microprocessor implemented data processing system that emulates a mainframe system. More particularly, this invention is directed to optimizing the performance of such a system insofar as the transfer of data between main memory and peripheral devices is concerned.
2. Description of the Prior Art
The emulation of "mainframe" data processing systems through the use of microprocessors has become a reality. A typical main frame data processing system would be any one of the System/370 (S/370) models available from International Business Machines Corporation. The Personal Computer XT/370, a "desktop" System/370, also available from International Business Machines Corporation, is one example of such a microprocessor implemented main frame. This particular desktop system is a hardware/software package that allows one to run System/370 application programs in a single user environment, to run as a terminal attached to a main frame host or to run in a stand-alone mode as a personal computer, as required by the particular application. There are, of course, similar systems available from other manufacturers, all of which systems incorporate many of the same functions as the Personal Computer XT/370 although the manner and means of implementation does differ, in varying degrees, from system to system.
Due to revolutionary advances in chip densities and packaging, which have been accompanied by significant reductions in costs, many main frame features can now be implemented directly in a desktop system, while other features require some hardware and/or software assistance in order to make them available. The introduction and use of more powerful microprocessors such as, for example, the 8086 and 8088 from Intel Corporation and the 68000 from Motorola Corporation, added further to the list of functions it would be possible to implement in a desktop mainframe. This new breed of microprocessors is fully capable of running a large, enriched instruction set, such as that of System/370, although several of these microprocessors, working in concert with the aid of additional hardware and/or software support, would be required to effect instruction execution in an acceptable time period. It will also be appreciated that presently available microprocessors, while remarkable for the functions they do offer, are not capable of providing all mainframe capability without system compromise.
Thus, as in all data processing system designs, various trade-offs are made in order to optimize the price and performance of these microprocessor implemented desktop mainframes. One particular trade-off problem is posed by the need or desire to utilize certain mainframe functions and features that would be particularly difficult to provide in a microprocessor implemented desktop mainframe. Another type of trade-off problem is posed by the requirement that all architectural constraints of the emulated mainframe be adhered to so that user programs can be run without concern. One specific implementation problem of concern, due in part to such trade-offs being made, is that of optimizing the operation of data transfer to and from peripheral devices.
In a data processing system implemented with one or more microprocessors and including a plurality of peripheral devices, that data path between main memory and the peripheral devices represents a potential performance problem. The peripherals are "slave" devices, that is, they have no built-in intelligence or memory access capabilities. Commands and data must be transferred to and from a peripheral by the host microprocessor. In those systems where the peripheral is a memory mapped device, there is control logic between the host microprocessor and the peripherals as well.
The control logic, among other functional responsibilities, decodes the address and control bus to determine if the host is transferring a command or data to or from a peripheral. If so, it then intercepts the bus and provides the proper control signals at the peripheral of interest to perform the data transfer. This means that data from memory must be first read by the host microprocessor into its internal storage area and then transferred to the peripheral. Similarly, results must be read from the peripheral into the internal storage area of the host microprocessor and then written into main memory therefrom. This operational data flow, via the host microprocessor's internal storage area, requires two host bus cycles to transfer one data element between main storage and a peripheral device.
In a microprocessor implemented mainframe, this data transfer approach will result in system performance degradation, particularly if the peripheral is a high usage device. Thus, while it would be possible to utilize standard data transfer arrangements and methodology in a microprocessor implemented mainframe data processing system, the performance penalties associated with that approach to the data handling are not acceptable.